Electrostatic discharge protection structure and chip

ABSTRACT

An electrostatic discharge protection structure and a chip are provided. The electrostatic discharge protection structure includes: a semiconductor substrate, an N-type well, a P-type well, a first N-type doped portion, a first P-type doped portion, a second P-type doped portion and a second N-type doped portion. The N-type well and the P-type well are located in the semiconductor substrate. The first N-type doped portion and the second P-type doped portion are located in the P-type well, and the first P-type doped portion and the second N-type doped portion are located in the N-well. The first N-type doped portion has a “T” shape structure, the first P-type doped portion has a “U” shape structure, and a part of the first N-type doped portion is located in a “U” shape opening of the first P-type doped portion.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of International Patent ApplicationNo. PCT/CN2022/104450 filed on Jul. 7, 2022, which claims priority toChinese patent application No. 202210731472.9 filed on Jun. 24, 2022.The entire contents of the prior applications are hereby incorporated byreference in their entirety.

BACKGROUND

A chip generally needs to be provided with an electrostatic discharge(ESD) protection circuit. The electrostatic discharge protection circuitis used to discharge static electricity in the chip to avoid damage to acore circuit in the chip under the action of static electricity.

At present, a layout area of an electrostatic discharge protectionstructure for forming the electrostatic discharge protection circuit islarge, which is not conducive to a design of the chip.

It should be noted that the information disclosed in the backgroundsection is only for enhancement of understanding of the background ofthe present disclosure, and therefore may contain information that doesnot form the prior art that is already known to a person of ordinaryskill in the art.

SUMMARY

The present disclosure relates to the field of semiconductortechnologies, and in particular, to an electrostatic dischargeprotection structure and a chip.

In a first aspect, the embodiments of the present disclosure provide anelectrostatic discharge protection structure. The electrostaticdischarge protection structure includes: a semiconductor substrate, anN-type well, a P-type well, a first N-type doped portion, a first P-typedoped portion, a second P-type doped portion, and a second N-type dopedportion. The N-type well is located in the semiconductor substrate, andthe P-type well is located in the semiconductor substrate. The firstN-type doped portion is located in the P-type well, and the first N-typedoped portion includes a first extension portion and a second extensionportion that are connected to each other. An orthographic projection ofthe first extension portion on a target projection plane extends along afirst direction, an orthographic projection of the second extensionportion on the target projection plane extends along a second direction,the target projection plane is parallel to a plane where thesemiconductor substrate is located, and the first direction intersectsthe second direction. The first P-type doped portion is located in theN-type well, and the first P-type doped portion includes a thirdextension portion, a fourth extension portion, and a fifth extensionportion connected between the third extension portion and the fourthextension portion. Both an orthographic projection of the thirdextension portion on the target projection plane and an orthographicprojection of the fourth extension portion on the target projectionplane extend along the second direction, the orthographic projection ofthe second extension portion on the target projection plane is locatedbetween the orthographic projection of the third extension portion onthe target projection plane and the orthographic projection of thefourth extension portion on the target projection plane, and anorthographic projection of the fifth extension portion on the targetprojection plane is located on a side of the orthographic projection ofthe second extension portion on the target projection plane away fromthe orthographic projection of the first extension portion on the targetprojection plane. The second P-type doped portion is located in theP-type well. An orthographic projection of the second P-type dopedportion on the target projection plane extends along the firstdirection, and is located on a side of an orthographic projection of thefirst N-type doped portion on the target projection plane away from anorthographic projection of the first P-type doped portion on the targetprojection plane. The second N-type doped portion is located in theN-type well. An orthographic projection of the second N-type dopedportion on the target projection plane extends along the firstdirection, and is located on a side of the orthographic projection ofthe first P-type doped portion on the target projection plane away fromthe orthographic projection of the first N-type doped portion on thetarget projection plane. The second P-type doped portion is electricallyconnected to the second N-type doped portion.

In a second aspect, the embodiments of the present disclosure provide achip. The chip includes the electrostatic discharge protection structurein the first aspect.

It is to be understood that the foregoing general description and thefollowing detailed description are exemplary and explanatory only andare not intended to limit the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments consistent with thepresent disclosure and together with the description serve to explainthe principles of the present disclosure. It is apparent that thedrawings in the following description are only some embodiments of thepresent disclosure, and for those of ordinary skill in the art, otherdrawings can also be obtained from these drawings without creativeeffort.

FIG. 1 is an equivalent circuit diagram of an exemplary embodiment of anelectrostatic discharge protection circuit of the present disclosure.

FIG. 2 is a structural layout of an exemplary embodiment of anelectrostatic discharge protection structure of the present disclosure.

FIG. 3 is a structural layout of well regions in FIG. 2 .

FIG. 4 is a structural layout of doped portions in FIG. 2 .

FIG. 5 is a cross-sectional view of the electrostatic dischargeprotection structure shown in FIG. 2 along the dashed line AA.

FIG. 6 is a structural layout of a deep well in FIG. 2 .

FIG. 7 is a structural diagram of an exemplary embodiment of a chip ofthe present disclosure.

FIG. 8 is a structural diagram of another exemplary embodiment of a chipof the present disclosure.

FIG. 9 is a structural diagram of a clamping circuit in an exemplaryembodiment of a chip of the present disclosure.

FIG. 10 is a structural diagram of a clamping circuit in anotherexemplary embodiment of a chip of the present disclosure.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference tothe accompanying drawings. Example embodiments, however, can beimplemented in various forms and should not be construed as beinglimited to the examples set forth herein. Rather, these embodiments areprovided so that the present disclosure will be more comprehensive andcomplete, and will fully convey the concept of example embodiments tothose skilled in the art. The same reference numerals in the drawingsdenote the same or similar structures, and thus their detaileddescriptions will be omitted.

Although relative terms such as “above” and “below” are used in thisspecification to describe the relative relationship of one component ofan icon to another component, these terms are used in this specificationonly for convenience, such as according to the direction of the exampledescribed in the accompany drawings. It will be appreciated that if thedevice of the icon is turned upside down, the component described as“above” will become the component described as “below”. Other relativeterms, such as “high”, “low”, “top”. “bottom”, “left” and “right”, arealso used to have similar meanings. When a structure is “above” otherstructures, it may mean that the structure is integrally located onother structures, or that the structure is “directly” arranged on otherstructure, or that the structure is “indirectly” arranged on otherstructures through another structure.

The terms “a”, “an” and “the” are used to indicate the existence of oneor more elements/components/etc. The terms “include/comprise” and “have”are used to indicate an open-ended inclusive meaning and mean thatadditional elements/components/etc. may exist in addition to the listedelements/components/etc.

An exemplary embodiment first provides an electrostatic dischargeprotection circuit. FIG. 1 is an equivalent circuit diagram of theexemplary embodiment of the electrostatic discharge protection circuitof the present disclosure. The electrostatic discharge protectioncircuit may include a PNP transistor Q1, an NPN transistor Q2, a firstdiode D1, and a second diode D2. An emitter of the PNP transistor Q1 isconnected to a first signal terminal V1, a base and a collector of thePNP transistor Q1 are connected to a node K; an emitter of the NPNtransistor Q2 is connected to a second signal terminal V2, and a baseand a collector of the NPN transistor Q2 are connected to the node K. Ananode of the first diode D1 is connected to the first signal terminalV1, a cathode of the first diode D1 is connected to the node K. An anodeof the second diode D2 is connected to the node K, and a cathode of thesecond diode D2 is connected to the second signal terminal V2.

The electrostatic discharge protection circuit can quickly dischargestatic electricity at the first signal terminal V1 to the second signalterminal V2. In a case that the static electricity occurs at the firstsignal terminal V1, the first diode D1 and the second diode D2 areturned on at first. Under an action of self-impedance of the first diodeD1, a voltage difference is generated between the first signal terminalV1 and the node K, and the voltage difference between the first signalterminal V1 and the node K triggers turning on of the PNP transistor Q1.Under an action of self-impedance of the second diode D2, a voltagedifference is generated between the second signal terminal V2 and thenode K, and the voltage difference between the second signal terminal V2and the node K triggers turning on of the NPN transistor Q2. Sincethreshold voltages of the first diode D1 and the second diode D2 aresmall, so that the electrostatic discharge protection circuit can have asmall trigger voltage.

As shown in FIGS. 2-5 , FIG. 2 is a structural layout of an exemplaryembodiment of an electrostatic discharge protection structure of thepresent disclosure, FIG. 3 is a structural layout of well regions inFIG. 2 , FIG. 4 is a structural layout of doped portions in FIG. 2 , andFIG. 5 is a cross-sectional view of the electrostatic dischargeprotection structure shown in FIG. 2 along the dashed line AA. Theelectrostatic discharge protection structure may include: asemiconductor substrate Psub, an N-type well NW, a P-type well PW, afirst N-type doped portion N1, a first P-type doped portion P1, a secondP-type doped portion P2, and a second N-type doped portion N2. TheN-type well NW is located in the semiconductor substrate Psub. and theP-type well PW is located in the semiconductor substrate Psub. The firstN-type doped portion N1 is located in the P-type well PW, and the firstN-type doped portion N1 includes a first extension portion N11 and asecond extension portion N12 that are connected to each other. Anorthographic projection of the first extension portion N11 on a targetprojection plane extends along a first direction X, and an orthographicprojection of the second extension portion N12 on the target projectionplane extends along a second direction Y. The target projection plane isparallel to a plane where the semiconductor substrate Psub is located.The first direction X intersects the second direction Y. For example,the first direction X is perpendicular to the second direction Y. Thefirst P-type doped portion P1 is located in the N-type well NW, and thefirst P-type doped portion P1 includes a third extension portion P13, afourth extension portion P14, and a fifth extension portion P15connected between the third extension portion P13 and the fourthextension portion P14. Both an orthographic projection of the thirdextension portion P13 on the target projection plane and an orthographicprojection of the fourth extension portion P14 on the target projectionplane extend along the second direction Y. The orthographic projectionof the second extension portion N12 on the target projection plane islocated between the orthographic projection of the third extensionportion P13 on the target projection plane and the orthographicprojection of the fourth extension portion P14 on the target projectionplane, and an orthographic projection of the fifth extension portion P15on the target projection plane is located on a side of the orthographicprojection of the second extension portion N12 on the target projectionplane away from the orthographic projection of the first extensionportion N11 on the target projection plane. The second P-type dopedportion P2 is located in the P-type well PW. An orthographic projectionof the second P-type doped portion P2 on the target projection planeextends along the first direction X, and is located on a side of anorthographic projection of the first N-type doped portion N1 on thetarget projection plane away from an orthographic projection of thefirst P-type doped portion P1 on the target projection plane. The secondN-type doped portion N2 is located in the N-type well NW. Anorthographic projection of the second N-type doped portion N1 on thetarget projection plane extends along the first direction X, and islocated on a side of the orthographic projection of the first P-typedoped portion P1 on the target projection plane away from theorthographic projection of the first N-type doped portion N1 on theplane where the semiconductor substrate Psub is located. The secondP-type doped portion P2 is electrically connected to the second N-typedoped portion N2.

The electrostatic discharge protection structure shown in FIG. 2 mayinclude the electrostatic discharge protection circuit shown in FIG. 1 .The first P-type doped portion P1 can be used to form the emitter of thePNP transistor Q1, the N-type well NW can be used to form the base ofthe PNP transistor Q1, and the P-type well PW can be used to form thecollector of the PNP transistor Q1. The first N-type doped portion N1can be used to form the emitter of the NPN transistor Q2, the P-typewell PW can be used to form the base of the NPN transistor Q2, and theN-type well NW can be used to form the collector of the NPN transistorQ2. The first P-type doped portion P1 can be used to form the anode ofthe first diode D1, and the N-type well NW can be used to form thecathode of the first diode D1. The P-type well PW can be used to formthe anode of the second diode D2, and the first N-type doped portion N1can be used to form the cathode of the second diode D2. The secondP-type doped portion P2 is electrically connected to the second N-typedoped portion N2, so as to connect the N-type well NW to the P-type wellPW, so that the cathode of the first diode D1 can be connected to theanode of the second diode D2.

In the present exemplary embodiment, the second P-type doped portion P2and the second N-type doped portion N2 may be connected by a conductiveline, and the conductive line may be formed on a surface of thesemiconductor substrate.

As shown in FIGS. 2-5 , in the present exemplary embodiment, the firstN-type doped portion N1 has a “T” shape structure, the first P-typedoped portion P1 has a “U” shape structure, and the second extensionportion N12 of the first N-type doped portion N1 is inserted into a “U”shape opening of the first P-type doped portion P1. In the presentexemplary embodiment, the first extension portion N11 and the secondextension portion N12 together form the emitter of the NPN transistorQ2, and the third extension portion P13, the fourth extension portionP14 and the fifth extension portion P15 together form the emitter of thePNP transistor Q1. Compared with the related art in which the N-typedoped portion and the P-type doped portion are arranged in a stripshape, the arrangement of the present disclosure can increase aneffective size of the PNP transistor Q1 and the NPN transistor Q2 in alimited space, thereby improving a speed of discharging the staticelectricity through a conductive channel formed by the PNP transistor Q1and the NPN transistor Q2, while reducing the trigger voltage. Inaddition, in the present exemplary embodiment, both the orthographicprojection of the second N-type doped portion N2 on the targetprojection plane and the orthographic projection of the second P-typedoped portion P2 on the target projection plane extend along the firstdirection X, and the second P-type doped portion P2 and the secondN-type doped portion N2 are respectively arranged on both sides of thePNP transistor Q1 and the NPN transistor Q2 in the second direction Y.Such an arrangement further reduces a size of the electrostaticdischarge protection structure in the first direction X.

It should be noted that the plane where the semiconductor substrate Psubis located can be understood as the plane where a side surface of thesemiconductor substrate Psub away from the first N-type doped portion N1is located. In the present exemplary embodiment, the semiconductorsubstrate Psub may be a P-type semiconductor substrate. In the presentexemplary embodiment, the P-type well formed in the P-type semiconductorsubstrate Psub may be directly formed by a part of the P-typesemiconductor substrate Psub. That is to say, the P-type well can beformed without further doping the P-type semiconductor substrate Psub.It should be understood that in other exemplary embodiments, thesemiconductor substrate may also be an N-type semiconductor substrate,and correspondingly, the N-type well formed in the N-type semiconductorsubstrate may be directly formed by a part of the N-type semiconductorsubstrate.

As shown in FIGS. 2-5 , the electrostatic discharge protection structuremay further include: a third N-type doped portion N3 and a third P-typedoped portion P3. The third N-type doped portion N3 is located in theP-type well PW, and an orthographic projection of the third N-type dopedportion N3 on the target projection plane and the orthographicprojection of the first N-type doped portion N1 on the target projectionplane are arranged at intervals in the first direction X. The thirdN-type doped portion N3 includes a sixth extension portion N36 and aseventh extension portion N37 that are connected to each other. Anorthographic projection of the sixth extension portion N36 on the targetprojection plane extends along the first direction X, and anorthographic projection of the seventh extension portion N37 on thetarget projection plane extends along the second direction Y The thirdP-type doped portion P3 is located in the N-type well NW. Anorthographic projection of the third P-type doped portion P3 on thetarget projection plane and the orthographic projection of the firstP-type doped portion P1 on the target projection plane are arranged atintervals in the first direction X. The third P-type doped portion P3includes an eighth extension portion P38, a ninth extension portion P39,and a tenth extension portion P310 connected between the eighthextension portion P38 and the ninth extension portion P39. Both anorthographic projection of the eighth extension portion P38 on thetarget projection plane and an orthographic projection of the ninthextension portion P39 on the target projection plane extend along thesecond direction Y, the orthographic projection of the seventh extensionportion N37 on the target projection plane is located between theorthographic projection of the eighth extension portion P38 on thetarget projection plane and the orthographic projection of the ninthextension portion P39 on the target projection plane, and anorthographic projection of the tenth extension portion P310 on thetarget projection plane is located on a side of the orthographicprojection of the seventh extension portion N37 on the target projectionplane away from the orthographic projection of the sixth extensionportion N36 on the target projection plane.

In the present exemplary embodiment, as shown in FIGS. 2-5 , theelectrostatic discharge protection structure may include twoelectrostatic discharge protection circuits (each is the electrostaticdischarge protection circuit shown in FIG. 1 ). The third P-type dopedportion P3 and the third N-type doped portion N3 can be used to form theother electrostatic discharge protection circuit. The third P-type dopedportion P3 can be used to form the emitter of the PNP transistor Q1, theN-type well NW can be used to form the base of the PNP transistor Q1,and the P-type well PW can be used to form the collector of the PNPtransistor Q1. The third N-type doped portion N3 can be used to form theemitter of the NPN transistor Q2, the P-type well PW can be used to formthe base of the NPN transistor Q2, and the N-type well NW can be used toform the collector of the NPN transistor Q2. The third P-type dopedportion P3 can be used to form the anode of the first diode D1, and theN-type well NW can be used to form the cathode of the first diode D1.The P-type well PW can be used to form the anode of the second diode D2,and the third N-type doped portion N3 can be used to form the cathode ofthe second diode D2.

In the present exemplary embodiment, as shown in FIGS. 2-5 , the sixthextension portion N36 and the seventh extension portion N37 togetherform the emitter of the NPN transistor Q2. The eighth extension portionP38, the ninth extension portion P39, and the tenth extension portionP310 together form the emitter of the PNP transistor Q1. Such anarrangement can also improve the speed of discharging the staticelectricity through the conductive channel formed by the PNP transistorQ1 and the NPN transistor Q2, while reducing a trigger voltage.

In the present exemplary embodiment, as shown in FIGS. 2-5 , theorthographic projection of the first P-type doped portion P1 on thetarget projection plane and the orthographic projection of the thirdP-type doped portion P3 on the target projection plane can be arrangedsymmetrically along the dashed line BB. The orthographic projection ofthe first N-type doped portion N1 on the target projection plane and theorthographic projection of the third N-type doped portion N3 on thetarget projection plane can be arranged symmetrically along the dashedline BB. An extension length of the orthographic projection of thesecond extension portion N12 on the target projection plane may begreater than an extension length of the orthographic projection of thefirst extension portion N11 on the target projection plane, and anextension length of the orthographic projection of the seventh extensionportion N37 on the target projection plane may be greater than anextension length of the orthographic projection of the sixth extensionportion N36 on the target projection plane.

In the present exemplary embodiment, as shown in FIGS. 2-5 , theorthographic projection of the second P-type doped portion P2 on thetarget projection plane is located on a side of the orthographicprojection of the third N-type doped portion N3 on the target projectionplane away from the orthographic projection of the third P-type dopedportion P3 on the target projection plane. The orthographic projectionof the second N-type doped portion N2 on the target projection plane islocated on a side of the orthographic projection of the third P-typedoped portion P3 on the target projection plane away from theorthographic projection of the third N-type doped portion N3 on thetarget projection plane.

In the present exemplary embodiment, as shown in FIGS. 2-5 , a part ofthe first extension portion N11 and at least part of the third extensionportion P13 are oppositely arranged in the second direction Y, andanother part of the first extension portion N11 and at least part of thefourth extension portion P14 are oppositely arranged in the seconddirection Y. A part of the sixth extension portion N36 and at least partof the eighth extension portion P38 are oppositely arranged in thesecond direction Y, and another part of the sixth extension portion N36and at least part of the ninth extension portion P39 are oppositelyarranged in the second direction Y. It should be noted that in thepresent exemplary embodiment, a structure A and a structure B areoppositely arranged in a direction, which can be understood as: an areacovered by infinite movement of an orthographic projection of thestructure A on the target projection plane in the direction coincideswith an area covered by infinite movement of an orthographic projectionof the structure B on the target projection plane in the direction. Suchan arrangement can further reduce the size of the electrostaticdischarge protection structure in the first direction X.

In the present exemplary embodiment, as shown in FIGS. 2-5 , at leastpart of the first extension portion N11 and at least part of the sixthextension portion N36 may be oppositely arranged in the first directionX. For example, the first extension portion N11 and the sixth extensionportion N36 may be oppositely arranged in the first direction X. Atleast part of the fifth extension portion PIS and at least part of thetenth extension portion P310 may be oppositely arranged in the firstdirection X. For example, the fifth extension portion P15 and the tenthextension portion P310 may be oppositely arranged in the first directionX. Such an arrangement can reduce the size of the electrostaticdischarge protection structure in the second direction Y.

In the present exemplary embodiment, as shown in FIGS. 2-5 , at leastpart of the first extension portion N11 and a part of the second P-typedoped portion P2 are oppositely arranged in the second direction Y, atleast part of the sixth extension portion N36 and another part of thesecond P-type doped portion P2 are oppositely arranged in the seconddirection Y. At least pan of the fifth extension portion P15 and a partof the second N-type doped portion N2 are oppositely arranged in thesecond direction Y, and at least part of the tenth extension portionP310 and another part of the second N-type doped portion N2 areoppositely arranged in the second direction Y. Such an arrangement cannot only ensure that the electrostatic discharge protection structurehas a small size in the first direction X, but also ensure that both thesecond N-type doped portion N2 and the second P-type doped portion P2have a certain extension length, thereby reducing a contact resistancebetween the cathode of the first diode D1 and the anode of the seconddiode D2.

In the present exemplary embodiment, as shown in FIGS. 2-5 , the P-typewell PW includes: a first well region PW1, a second well region PW2, anda third well region PW3. An orthographic projection of the first wellregion PW1 on the target projection plane extends along the firstdirection X. The second well region PW2 is connected to the first wellregion PW1, and an orthographic projection of the second well region PW2on the target projection plane extends along the second direction Y. Thethird well region PW3 is connected to the first well region PW1, anorthographic projection of the third well region PW3 on the targetprojection plane extends along the second direction Y, and theorthographic projection of the third well region PW3 on the targetprojection plane and the orthographic projection of the second wellregion PW2 on the target projection plane are located on a same side ofthe orthographic projection of the first well region PW1 on the targetprojection plane. The first extension portion N11, the sixth extensionportion N36 and the second P-type doped portion P2 are located in thefirst well region PW1, the second extension portion N12 is located inthe second well region PW2, and the seventh extension portion N37 islocated in the third well region PW3.

In the present exemplary embodiment, as shown in FIGS. 2-5 , theelectrostatic discharge protection structure may further include: anannular doped portion PC. An orthographic projection of the annulardoped portion PC on the target projection plane surrounds anorthographic projection of the N-type well NW on the target projectionplane and an orthographic projection of the P-type well PW on the targetprojection plane. A doping type of the annular doped portion PC is thesame as a doping type of the semiconductor substrate Psub. The annulardoped portion PC can be connected to a stable power supply terminal. Forexample, the annular doped portion PC can be grounded. Such anarrangement can electrically isolate the electrostatic dischargeprotection structure from other structures on the semiconductorsubstrate.

In the present exemplary embodiment, as shown in FIG. 5 , adjacent dopedportions may be isolated by an isolation wall (i.e., shallow trenchisolation, STI).

In the present exemplary embodiment, as shown in FIGS. 2-6 , FIG. 6 is astructural layout of a deep well in FIG. 2 . The orthographic projectionof the N-type well NW on the target projection plane surrounds theorthographic projection of the P-type well PW on the target projectionplane. The semiconductor substrate Psub may be a P-type semiconductorsubstrate. The electrostatic discharge protection structure may alsoinclude an N-type deep well DNW. The N-type deep well DNW is isolatedbetween the semiconductor substrate Psub and the P-type well PW. TheN-type deep well DNW can form a PN junction with the P-typesemiconductor substrate, thereby improving the problem of currentleakage from the P-type well PW to the semiconductor substrate Psub. Itshould be understood that in other exemplary embodiments, in a case thatthe semiconductor substrate is an N-type semiconductor substrate, theelectrostatic discharge protection structure may include a P-type deepwell. The P-type deep well may be isolated between the N-type well andthe N-type semiconductor substrate Psub, and the P-type deep well canform a PN junction with the N-type well, thereby also improving theproblem of current leakage from the N-type well to the semiconductorsubstrate Psub. In addition, the deep well can also play a role of noiseshielding for components in the N-type well NW and the P-type well PW.

In the present exemplary embodiment, a doping concentration of a dopedwell (e.g., the P-type well, the N-type well, the N-type deep well) maybe less than a doping concentration of a doped portion (e.g., the firstN-type doped portion, the first P-type doped portion, the second N-typedoped portion, the second P-type doped portion, the third N-type dopedportion, the third P-type doped portion, the annular doped portion).

In other exemplary embodiments, the electrostatic discharge protectionstructure may only include one electrostatic discharge protectioncircuit shown in FIG. 1 , and correspondingly, the electrostaticdischarge protection structure may not include the third P-type dopedportion P3 and the third N-type doped portion N3.

An exemplary embodiment further provides a chip. The chip may includethe above-mentioned electrostatic discharge protection structure.

In the present exemplary embodiment, the chip may include a firstterminal and a second terminal. The first terminal is connected to thefirst N-type doped portion N1, and the second terminal is connected tothe first P-type doped portion P1. In the present exemplary embodiment,the chip may include a high level power supply terminal, a low levelpower supply terminal, and a signal transmission terminal. The firstterminal may be the high level power supply terminal, and the secondterminal may be the signal transmission terminal. Alternatively, thefirst terminal may be the signal transmission terminal, and the secondterminal may be the low level power supply terminal. Alternatively, thefirst terminal may be the high level power supply terminal, and thesecond terminal may be the low level power supply terminal. The signaltransmission terminal may include at least one of a signal inputterminal or a signal output terminal.

FIG. 7 is a structural diagram of an exemplary embodiment of a chip ofthe present disclosure. The chip may include a high level power supplyterminal Vdd, a low level power supply terminal Vss, a signaltransmission terminal, and a core processing circuit CT. The signaltransmission terminal may include a signal output terminal OUT and asignal input terminal IN. In the present exemplary embodiment, the chipmay include a plurality of electrostatic discharge protection structures(each is the electrostatic discharge protection structure shown in FIG.2 ), and the plurality of electrostatic discharge protection structuresmay include: a first electrostatic discharge protection structure ESD1and a second electrostatic discharge protection structure ESD2. Thefirst P-type doped portion and the third N-type doped portion of thefirst electrostatic discharge protection structure ESD1 are connected tothe signal input terminal IN, the first N-type doped portion of thefirst electrostatic discharge protection structure ESD1 is connected tothe high level power supply terminal Vdd, and the third P-type dopedportion of the first electrostatic discharge protection structure ESD1is connected to the low level power supply terminal Vss. The firstP-type doped portion and the third N-type doped portion of the secondelectrostatic discharge protection structure ESD2 are connected to thesignal output terminal OUT, the first N-type doped portion of the secondelectrostatic discharge protection structure ESD2 is connected to thehigh level power supply terminal Vdd, and the third P-type doped portionof the second electrostatic discharge protection structure ESD2 isconnected to the low level power supply terminal Vss. It should be notedthat the low level power supply terminal Vss may be a ground terminal ofthe chip where the electrostatic discharge protection structure islocated, and the high level power supply terminal Vdd may be a powersupply terminal of the chip where the electrostatic discharge protectionstructure is located.

The low level power supply terminal Vss can discharge static electricityto the signal input terminal IN through the first electrostaticdischarge protection structure ESD1. The signal input terminal IN candischarge static electricity to the high level power supply terminal Vddthrough the first electrostatic discharge protection structure ESD1. Thesignal output terminal OUT can discharge static electricity to the highlevel power supply terminal Vdd through the second electrostaticdischarge protection structure ESD2. The low level power supply terminalVss can discharge static electricity to the signal output terminal OUTthrough the second electrostatic discharge protection structure ESD2.

FIG. 8 is a structural diagram of another exemplary embodiment of a chipof the present disclosure. The chip may also include a high level powersupply terminal Vdd, a low level power supply terminal Vss, a signaltransmission terminal, and a core processing circuit CT. The signaltransmission terminal includes a signal output terminal OUT and a signalinput terminal IN. In the present exemplary embodiment, the chip mayinclude a first electrostatic discharge protection structure ESD1, asecond electrostatic discharge protection structure ESD2, a thirdelectrostatic discharge protection structure ESD3, and a fourthelectrostatic discharge protection structure ESD4. At least part of thefirst electrostatic discharge protection structure ESD1, the secondelectrostatic discharge protection structure ESD2, the thirdelectrostatic discharge protection structure ESD3 and the fourthelectrostatic discharge protection structure ESD4 may be theabove-mentioned electrostatic discharge protection structure. Theabove-mentioned electrostatic discharge protection structure may includeone or two electrostatic discharge protection circuits (each is theelectrostatic discharge protection circuit shown in FIG. 1 ). Forexample, each of the second electrostatic discharge protection structureESD2 and the fourth electrostatic discharge protection structure ESD4may have the structure as shown in FIG. 2 . The first P-type dopedportion and the third N-type doped portion of the second electrostaticdischarge protection structure ESD2 are connected to the signal inputterminal IN, and the first N-type doped portion and the third P-typedoped portion of the second electrostatic discharge protection structureESD2 are connected to the low level power supply terminal Vss. The firstP-type doped portion and the third N-type doped portion of the fourthelectrostatic discharge protection structure ESD4 are connected to thesignal output terminal OUT, the first N-type doped portion and the thirdP-type doped portion of the fourth electrostatic discharge protectionstructure ESD4 are connected to the low level power supply terminal Vss.The low level power supply terminal Vss and the signal input terminal INcan realize the discharging of static electricity in both directionsthrough the second electrostatic discharge protection structure ESD2.The low level power supply terminal Vss and the signal output terminalOUT can realize the discharging of static electricity in both directionsthrough the fourth electrostatic discharge protection structure ESD4.The first electrostatic discharge protection structure ESD1 and thethird electrostatic discharge protection structure ESD3 may includediode structures. An anode of the diode in the first electrostaticdischarge protection structure ESD1 is connected to the signal inputterminal IN, and a cathode of the diode in the first electrostaticdischarge protection structure ESD1 is connected to the high level powersupply terminal Vdd. An anode of the diode in the third electrostaticdischarge protection structure ESD3 is connected to the signal outputterminal OUT, and a cathode of the diode in the third electrostaticdischarge protection structure ESD3 is connected to the high level powersupply terminal Vdd.

In the present exemplary embodiment, the chip may be a dynamic randomaccess memory or a static random access memory. It should be understoodthat the chip can also be other chips, the chip can also include othersignal transmission terminals, and other signal terminals can alsodischarge static electricity through the above-mentioned electrostaticdischarge protection structure(s).

As shown in FIG. 7 and FIG. 8 , the chip may further include a clampingcircuit pcp. FIG. 9 is a structural diagram of a clamping circuit in anexemplary embodiment of a chip of the present disclosure. The clampingcircuit pcp may include a capacitor C, a resistor R, and an N-typetransistor NM. The capacitor C is connected between the high level powersupply terminal Vdd and a node M, and the resistor R is connectedbetween the node M and the low level power supply terminal Vss. A gateelectrode of the N-type transistor NM is connected to the node M, afirst electrode of the N-type transistor NM is connected to the highlevel power supply terminal Vdd, a second electrode of the N-typetransistor NM is connected to the low level power supply terminal Vss,and a semiconductor substrate of the N-type transistor NM can beconnected to the second electrode of the N-type transistor NM. Whenstatic electricity occurs at the high level power supply terminal Vdd, avoltage of the high level power supply terminal Vdd rises, under thecoupling effect of the capacitor C, a potential of the node M rises, theN-type transistor NM is turned on, and the high level power supplyterminal Vdd can discharge static electricity to the low level powersupply terminal Vss through the N-type transistor NM. It should beunderstood that in other exemplary embodiments, the semiconductorsubstrate of the N-type transistor NM can also be connected to the gateelectrode of the N-type transistor NM, so that the N-type transistor NMcan form a substrate driving transistor which can be used to dischargelarge electrostatic currents.

FIG. 10 is a structural diagram of a clamping circuit in anotherexemplary embodiment of a chip of the present disclosure. The clampingcircuit may include a capacitor C, a resistor R, a P-type transistor PM,a first N-type transistor NM1, and a second N-type transistor NM2. Theresistor R is connected between a high level power supply terminal Vddand a first node G1. The capacitor C is connected between the first nodeG1 and a low level power supply terminal Vss. A first electrode of theP-type transistor PM is connected to the high level power supplyterminal Vdd, a second electrode of the P-type transistor PM isconnected to a second node G2 and a gate electrode of the P-typetransistor PM is connected to the first node G1. A first electrode ofthe first N-type transistor NM1 is connected to the second node G2, asecond electrode of the first N-type transistor NM1 is connected to thelow level power supply terminal Vss, and a gate electrode of the firstN-type transistor NM1 is connected to the first node G1. A firstelectrode of the second N-type transistor NM2 is connected to the highlevel power supply terminal Vdd, a second electrode of the second N-typetransistor NM2 is connected to the low level power supply terminal Vss,and a gate electrode of the second N-type transistor NM2 is connected tothe second node G2. When static electricity occurs at the high levelpower supply terminal Vdd, the static electricity forms a high-frequencyalternating current between the high level power supply terminal Vdd andthe low level power supply terminal Vss. Under the action of thehigh-frequency alternating current, an impedance of the capacitor Cdecreases, a potential of the first node G1 is pulled down by the lowlevel power supply terminal Vss, the P-type transistor PM is turned on,the high level power supply terminal Vdd inputs a high level signal tothe second node G2, the second N-type transistor NM2 is turned on, andthe high level power supply terminal Vdd discharges static electricityto the low level power supply terminal Vss through the second N-typetransistor NM2.

The present exemplary embodiment skillfully integrates the electrostaticdischarge protection structure and the clamping circuit to realize theelectrostatic discharge protection of the full chip. The electrostaticdischarge protection structure adopts a new layout method, which has thecharacteristics of small area, low trigger voltage, strong anti-latchcapability, high electrostatic discharge protection capability, andsmall capacitance. The electrostatic discharge protection structure canbe used for electrostatic discharge protection of low-voltage high-speedintegrated circuit products.

Those skilled in the art will easily think of other embodiments of thedisclosure after considering the specification and practicing thecontents disclosed herein. The present disclosure is intended to coverany variant, usage or adaptation of the present disclosure, whichfollows the general principles of the present disclosure and includesthe common knowledge or conventional technical means in the technicalfield not disclosed in the present disclosure. The specification andembodiments are to be considered exemplary only, and the true scope andspirit of the present disclosure are indicated by the claims.

It is to be understood that the present disclosure is not limited to theprecise structures described above and illustrated in the accompanyingdrawings, and that various modifications and changes may be made withoutdeparting from its scope. The scope of the present disclosure is limitedonly by the appended claims.

1. An electrostatic discharge protection structure, comprising: asemiconductor substrate; an N-type well located in the semiconductorsubstrate; a P-type well located in the semiconductor substrate; a firstN-type doped portion located in the P-type well, wherein the firstN-type doped portion comprises a first extension portion and a secondextension portion that are connected to each other; wherein anorthographic projection of the first extension portion on a targetprojection plane extends along a first direction, an orthographicprojection of the second extension portion on the target projectionplane extends along a second direction, the target projection plane isparallel to a plane where the semiconductor substrate is located, andthe first direction intersects the second direction: a first P-typedoped portion located in the N-type well, wherein the first P-type dopedportion comprises a third extension portion, a fourth extension portion,and a fifth extension portion connected between the third extensionportion and the fourth extension portion; wherein both an orthographicprojection of the third extension portion on the target projection planeand an orthographic projection of the fourth extension portion on thetarget projection plane extend along the second direction, theorthographic projection of the second extension portion on the targetprojection plane is located between the orthographic projection of thethird extension portion on the target projection plane and theorthographic projection of the fourth extension portion on the targetprojection plane, and an orthographic projection of the fifth extensionportion on the target projection plane is located on a side of theorthographic projection of the second extension portion on the targetprojection plane away from the orthographic projection of the firstextension portion on the target projection plane; a second P-type dopedportion located in the P-type well, wherein an orthographic projectionof the second P-type doped portion on the target projection planeextends along the first direction, and is located on a side of anorthographic projection of the first N-type doped portion on the targetprojection plane away from an orthographic projection of the firstP-type doped portion on the target projection plane; and a second N-typedoped portion located in the N-type well, wherein an orthographicprojection of the second N-type doped portion on the target projectionplane extends along the first direction, and is located on a side of theorthographic projection of the first P-type doped portion on the targetprojection plane away from the orthographic projection of the firstN-type doped portion on the target projection plane; wherein the secondP-type doped portion is electrically connected to the second N-typedoped portion.
 2. The electrostatic discharge protection structure ofclaim 1, further comprising: a third N-type doped portion located in theP-type well, wherein an orthographic projection of the third N-typedoped portion on the target projection plane and the orthographicprojection of the first N-type doped portion on the target projectionplane are arranged at intervals in the first direction; wherein thethird N-type doped portion comprises a sixth extension portion and aseventh extension portion that are connected to each other, anorthographic projection of the sixth extension portion on the targetprojection plane extends along the first direction, and an orthographicprojection of the seventh extension portion on the target projectionplane extends along the second direction; and a third P-type dopedportion located in the N-type well, wherein an orthographic projectionof the third P-type doped portion on the target projection plane and theorthographic projection of the first P-type doped portion on the targetprojection plane are arranged at intervals in the first direction;wherein the third P-type doped portion comprises an eighth extensionportion, a ninth extension portion, and a tenth extension portionconnected between the eighth extension portion and the ninth extensionportion, both an orthographic projection of the eighth extension portionon the target projection plane and an orthographic projection of theninth extension portion on the target projection plane extend along thesecond direction, the orthographic projection of the seventh extensionportion on the target projection plane is located between theorthographic projection of the eighth extension portion on the targetprojection plane and the orthographic projection of the ninth extensionportion on the target projection plane, and an orthographic projectionof the tenth extension portion on the target projection plane is locatedon a side of the orthographic projection of the seventh extensionportion on the target projection plane away from the orthographicprojection of the sixth extension portion on the target projectionplane; the orthographic projection of the second P-type doped portion onthe target projection plane is located on a side of the orthographicprojection of the third N-type doped portion on the target projectionplane away from the orthographic projection of the third P-type dopedportion on the target projection plane; and the orthographic projectionof the second N-type doped portion on the target projection plane islocated on a side of the orthographic projection of the third P-typedoped portion on the target projection plane away from the orthographicprojection of the third N-type doped portion on the target projectionplane.
 3. The electrostatic discharge protection structure of claim 2,wherein a part of the first extension portion and at least part of thethird extension portion are oppositely arranged in the second direction,and another part of the first extension portion and at least part of thefourth extension portion are oppositely arranged in the seconddirection; and a part of the sixth extension portion and at least partof the eighth extension portion are oppositely arranged in the seconddirection, and another part of the sixth extension portion and at leastpart of the ninth extension portion are oppositely arranged in thesecond direction.
 4. The electrostatic discharge protection structure ofclaim 2, wherein the P-type well comprises: a first well region, whereinan orthographic projection of the first well region on the targetprojection plane extends along the first direction; a second well regionconnected to the first well region, wherein an orthographic projectionof the second well region on the target projection plane extends alongthe second direction; and a third well region connected to the firstwell region, wherein an orthographic projection of the third well regionon the target projection plane extends along the second direction, andthe orthographic projection of the third well region on the targetprojection plane and the orthographic projection of the second wellregion on the target projection plane are located on a same side of theorthographic projection of the first well region on the targetprojection plane; wherein the first extension portion, the sixthextension portion and the second P-type doped portion are located in thefirst well region, the second extension portion is located in the secondwell region, and the seventh extension portion is located in the thirdwell region.
 5. The electrostatic discharge protection structure ofclaim 2, wherein at least part of the first extension portion and a partof the second P-type doped portion are oppositely arranged in the seconddirection, and at least part of the sixth extension portion and anotherpart of the second P-type doped portion are oppositely arranged in thesecond direction; and at least part of the fifth extension portion and apart of the second N-type doped portion are oppositely arranged in thesecond direction, and at least part of the tenth extension portion andanother part of the second N-type doped portion are oppositely arrangedin the second direction.
 6. The electrostatic discharge protectionstructure of claim 1, wherein an orthographic projection of the N-typewell on the target projection plane surrounds an orthographic projectionof the P-type well on the target projection plane; wherein thesemiconductor substrate is a P-type semiconductor substrate, and theelectrostatic discharge protection structure further comprises: anN-type deep well isolated between the semiconductor substrate and theP-type well.
 7. The electrostatic discharge protection structure ofclaim 1, further comprising: an annular doped portion, wherein anorthographic projection of the annular doped portion on the targetprojection plane surrounds an orthographic projection of the N-type wellon the target projection plane and an orthographic projection of theP-type well on the target projection plane; and a doping type of theannular doped portion and a doping type of the semiconductor substrateare identical.
 8. A chip, comprising the electrostatic dischargeprotection structure of claim
 1. 9. The chip of claim 8, furthercomprising a first terminal and a second terminal, wherein the firstterminal is connected to the first N-type doped portion, and the secondterminal is connected to the first P-type doped portion.
 10. The chip ofclaim 9, further comprising a high level power supply terminal, a lowlevel power supply terminal, and a signal transmission terminal, whereinthe first terminal is the high level power supply terminal, and thesecond terminal is the signal transmission terminal; or the firstterminal is the signal transmission terminal, and the second terminal isthe low level power supply terminal; or the first terminal is the highlevel power supply terminal, and the second terminal is the low levelpower supply terminal.
 11. The chip of claim 8, further comprising a lowlevel power supply terminal and a signal transmission terminal, whereinin a case that the electrostatic discharge protection structurecomprises a third P-type doped portion and a third N-type doped portion,the signal transmission terminal is connected to the first P-type dopedportion and the third N-type doped portion, and the low level powersupply terminal is connected to the first N-type doped portion and thethird P-type doped portion.
 12. The chip of claim 11, wherein the signaltransmission terminal comprises a signal output terminal and a signalinput terminal, the chip comprises a plurality of the electrostaticdischarge protection structures, and the plurality of the electrostaticdischarge protection structures comprises: a first electrostaticdischarge protection structure, wherein the first P-type doped portionand the third N-type doped portion of the first electrostatic dischargeprotection structure are connected to the signal input terminal, and thefirst N-type doped portion and the third P-type doped portion of thefirst electrostatic discharge protection structure are connected to thelow level power supply terminal; and a second electrostatic dischargeprotection structure, wherein the first P-type doped portion and thethird N-type doped portion of the second electrostatic dischargeprotection structure are connected to the signal output terminal, andthe first N-type doped portion and the third P-type doped portion of thesecond electrostatic discharge protection structure are connected to thelow level power supply terminal.
 13. The chip of claim 8, furthercomprising a high level power supply terminal, a low level power supplyterminal, and a signal transmission terminal, wherein in a case that theelectrostatic discharge protection structure comprises a third P-typedoped portion and a third N-type doped portion, the signal transmissionterminal is connected to the first P-type doped portion and the thirdN-type doped portion, the high level power supply terminal is connectedto the first N-type doped portion, and the low level power supplyterminal is connected to the third P-type doped portion.
 14. The chip ofclaim 13, wherein the signal transmission terminal comprises a signaloutput terminal and a signal input terminal, the chip comprises aplurality of the electrostatic discharge protection structures, and theplurality of the electrostatic discharge protection structurescomprises: a first electrostatic discharge protection structure, whereinthe first P-type doped portion and the third N-type doped portion of thefirst electrostatic discharge protection structure are connected to thesignal input terminal, the first N-type doped portion of the firstelectrostatic discharge protection structure is connected to the highlevel power supply terminal, and the third P-type doped portion of thefirst electrostatic discharge protection structure is connected to thelow level power supply terminal; and a second electrostatic dischargeprotection structure, wherein the first P-type doped portion and thethird N-type doped portion of the second electrostatic dischargeprotection structure are connected to the signal output terminal, thefirst N-type doped portion of the second electrostatic dischargeprotection structure is connected to the high level power supplyterminal, and the third P-type doped portion of the second electrostaticdischarge protection structure is connected to the low level powersupply terminal.
 15. The chip of claim 8, wherein the chip is a dynamicrandom access memory or a static random access memory.